Complex Instruction Set Architecture, and RISC or Reduced Instruction Set ComputerToday we have two dominant computer architectures, complex instruction set architecture or CISCand reduced instruction set computer, or RISC. CISC is typified by what is referred to as the von Neumann Architecture, invented by John von Neumann of Princeton University. In the von Neu-mann architecture, both the instruction memory and the data memory share the same physical memory space. This can lead to a condition called the von Neumannbottleneck, where the same ex-ternal address and data busses must serve double duty, transferring instructions from memory to the processor for program execution, and moving data to and from memory for the storage and retrieval of program variables. When the processor is moving data, it can’t fetch the next instruc-tion, and vice versa. The solution to this dilemma, as we shall see later, is the introduction of separate on-chip instruction and data caches. Motorola’s 68000 processor and its successors, and Intel’s 8086 processor and its successors are all characteristic of CISC processors. We’ll take a more in-depth look at the differences between CISC and RISC processors again later when we study pipelining